The present invention generally relates to an input/output (I/O) circuit, and more particularly to an ElectroStatic Discharge (ESD) current bypass module in an I/O circuit that tolerates a high voltage input.
FIG. 1 illustrates a conventional ESD current bypass circuit 10. A pad 11 is electrically connected to an internal circuit 12 via a node 16. A first diode 14 is connected between the node 16 and an I/O power supply 13 having a reference voltage Vdd. A second diode 15 is connected between ground and the node 16. The first diode 14 and second diode 15 clamp the voltage level between the pad 11 and the internal circuit 12 to a certain range. In a normal operation mode, an input signal that falls in this voltage range travels directly from the pad 11 to the internal circuit 12. In an ESD event, an ESD current input from the pad 11 would have a voltage level exceeding the clamped voltage range, and dissipate via the first diode 14 to the I/O power supply 13 or via the second diode 15 to ground. Thus, the internal circuit 12 is protected from such high voltage input due to the ESD event.
One problem of the conventional ESD current bypass circuit 10 is that it cannot operate normally when an operational signal input from the pad 11 has a voltage level Vpad higher than Vdd. If Vpad is higher than Vdd, the first diode 14 will be forward biased and a leakage current will occur between the node 16 and the I/O power supply 13. This would cause Vpad dropping to a lower voltage level, and therefore distort the input signal. As it happens often that high voltage devices and low voltage devices are used in the same integrated circuit, the low voltage devices may be exposed to high voltage signals. The low voltage device may not accommodate the high voltage signals. As such, the problems of leakage current and signal distortion become increasingly troublesome.
FIG. 2 illustrates another conventional ESD current bypass circuit 20. A pad 21 is connected to an internal circuit 24 via a node 30. A PMOS transistor 22 is connected between the node 30 and an I/O power supply 29 having a voltage Vdd. A PMOS transistor 25 is connected between the I/O power supply 29 and the gate of the PMOS transistor 22. A PMOS transistor 26 that is used as a capacitor is connected between the I/O power supply 29 and ground via a resistor RP. An NMOS transistor 23 is connected between the node 30 and ground. An NMOS transistor 27 is connected between ground and the gate of the transistor 23. An NMOs transistor 28 that is used as a capacitor is connected between ground and Vdd via a resistor RN.
The conventional ESD current bypass circuit 20 also has the problems of leakage current and signal distortion, when an operational signal input from the pad 21 has a voltage level Vpad higher than Vdd. For example, assuming Vpad is 5.0 V and Vdd is 3.3 V, the voltage level on wire pp1 is 0.0 V as it is connected to ground. Thus, the PMOS transistor 25 conducts, and wire pp2 has a voltage level of 3.3V, the same as Vdd. For the PMOS transistor 22, the voltage difference between its gate and source is −1.7 V (3.3 V–5.0 V) and the voltage difference between the gate and drain is 0.0 V. The PMOS transistor 22 cannot be completely turned off and there would be leakage current between the node 30 and I/O power supply 29. This would distort the 5.0 V signal input from the pad 21.
In addition, the ESD current bypass circuit 20 has the problem of voltage overstress on the gate oxide of the NMOS transistor 23. Since the voltage level of the gate of transistor 23 constantly remains at 0 V, no matter whether the signal input from the pad 21 is a high voltage or low voltage signal. Due to the voltage overstress, the gate oxide may fail over a period of time. This causes potential reliability issues.
What is needed is an ESD bypass I/O circuit that tolerates high voltage signals and is less susceptible to voltage overstress issues.